Explore digital design, HDL, and FPGA implementation, offering a strong foundation in Very Large Scale Integration.
Module Name |
Description |
Advanced Digital Design |
· Introduction to Digital Design and Switching Algebra · Number Systems and Binary Codes · Minimization of Switching Functions · Combinational Circuit Design · Sequential Circuit Design · Controller Design Using FSMs & ASMs · Design of CPLDs (PAL, PLA, PROM) · Design Examples & Case Studies |
Hardware Description Language (Verilog HDL) |
· Introduction to Verilog HDL & Hierarchical Modeling Concepts · Lexical Conventions & Data Types · System Tasks & Compiler Directives · Modules, Ports and Module Instantiation Methods · Combinational Logic Design and Sequential Logic Design · Modeling Methods. · Design Verification Using Test Benches |
FPGA Architecture And Prototyping |
· Introduction to Programmable Logic and FPGA · Popular CPLD & FPGA Families · Architecture of Popular Xilinx and Altera FPGAS · FPGA Design Flow · ASIC Design Flow · Logic Synthesis for FPGA · Static Timing Analysis |
CMOS Base Design Concepts |
· Introduction to CMOS · MOS Fundamentals · MOSFET VI Characteristics · CMOS Inverter Design · Combinational Logic Design · Layouts and Stick Diagram · Fabrication Process · Sequential Logic Design |
CMOS Analog VLSI Design |
· Introduction to Analog Ic Design · Short Channel Effects · Current Mirrors · Amplifiers · Feedback Circuits · Frequency Response of Amplifiers · Noise · Operational Amplifier Stability And Frequency Compensation |
Design For Testability |
· Fault Types and Models · Controllability & Observability · Ad Hoc Testable Design Techniques · Built-In Self Test Techniques |
Low Power VLSI Design |
· Low Power CMOS Logic Circuits: Over View of Power Consumption · Low-Power Design Through Voltage Scaling · Interconnect Design, Power Grid And Clock Design |
Final Project |
· FIFO · Traffic Light controller · Elevator Controller · PISO/SIPO · Hrs:Min:Sec Watch · RISC Processor |
1 Subject
62 Courses • 33756 Students
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